In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uni...
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonia...
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops do not ...
Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alo...
— This paper analyzes the average bit error rate (BER) performance of singular value decomposition-based multiple-input multiple-output systems with channel estimation error and ...
Edward K. S. Au, Shi Jin, Matthew R. McKay, Wai Ho...
— In interference-limited wireless cellular systems, interference avoidance and interference averaging are widely adopted to combat co-channel interference. In different types of...