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GLVLSI
2010
IEEE
136views VLSI» more  GLVLSI 2010»
14 years 24 days ago
Thermal-aware compilation for system-on-chip processing architectures
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
Mohamed M. Sabry, José L. Ayala, David Atie...
DAC
2008
ACM
14 years 8 months ago
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Mem...
IPPS
2005
IEEE
14 years 1 months ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...
MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
14 years 1 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
PDPTA
2000
13 years 9 months ago
An Economy Driven Resource Management Architecture for Global Computational Power Grids
The growing computational power requirements of grand challenge applications has promoted the need for linking highperformance computational resources distributed across multiple ...
Rajkumar Buyya, David Abramson, Jonathan Giddy