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DFT
2004
IEEE
101views VLSI» more  DFT 2004»
13 years 11 months ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
DAC
2004
ACM
13 years 11 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
IWIA
2006
IEEE
14 years 1 months ago
Modeling and Execution of Complex Attack Scenarios using Interval Timed Colored Petri Nets
The commonly used flaw hypothesis model (FHM) for performing penetration tests provides only limited, highlevel guidance for the derivation of actual penetration attempts. In thi...
Ole Martin Dahl, Stephen D. Wolthusen
ICIAP
2007
ACM
14 years 8 months ago
A Consistency Result for the Normalized Eight-Point Algorithm
A recently proposed argument to explain the improved performance of the eight-point algorithm that results from using normalized data [IEEE Trans. Pattern Anal. Mach. Intell., 25(...
Wojciech Chojnacki, Michael J. Brooks
HPCC
2007
Springer
14 years 1 months ago
Parallel Performance Prediction for Multigrid Codes on Distributed Memory Architectures
We propose a model for describing the parallel performance of multigrid software on distributed memory architectures. The goal of the model is to allow reliable predictions to be m...
Giuseppe Romanazzi, Peter K. Jimack