Designs for Reducing Test Time of Distributed Small Embedded SRAMs

This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improvements are mainly two-fold. On one hand, the testing of time-consuming Data Retention Faults (DRFs), that is neglected by the test architecture in [4, 5], is now considered and performed via a DFT technique referred to as the "No Write Recovery Test Mode (NWRTM)". On the other hand, a parallel Local Response Analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained in [4, 5], with a negligible area cost.

• Type: Conference
• Year: 2004
• Where: DFT
• Authors: Baosheng Wang, Yuejian Wu, André Ivanov
• Keywords: DFT 2004, Proposed Test Architecture, Test Architecture, Test Time, VLSI