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SIGCOMM
2009
ACM
14 years 3 months ago
Crossbow: a vertically integrated QoS stack
This paper describes a new architecture which addresses Quality of Service (QoS) by creating unique flows for applications, services, or subnets. A flow is a dedicated and indep...
Sunay Tripathi, Nicolas Droux, Thirumalai Srinivas...
IEEEPACT
2008
IEEE
14 years 3 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
CLUSTER
2007
IEEE
14 years 3 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...
COMSWARE
2007
IEEE
14 years 3 months ago
Situation-Aware Software Engineering for Sensor Networks
—Sensor networks represent a new frontier in technology that holds the promise of unprecedented levels of autonomy in the execution of complex dynamic missions by harnessing the ...
Vir V. Phoha, Shashi Phoha
ISCAS
2007
IEEE
94views Hardware» more  ISCAS 2007»
14 years 3 months ago
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
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