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» Domain Reduction for the Circuit Constraint
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CP
2005
Springer
14 years 29 days ago
Encoding HTN Planning as a Dynamic CSP
Abstract. Constraint satisfaction problems provide strong formalism for modeling variety of real life problems. This paper presents a work currently in progress of which the goal i...
Pavel Surynek, Roman Barták
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 11 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 4 months ago
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzh...
ASPDAC
2008
ACM
122views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Total power optimization combining placement, sizing and multi-Vt through slack distribution management
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
Tao Luo, David Newmark, David Z. Pan
CAV
2008
Springer
125views Hardware» more  CAV 2008»
13 years 9 months ago
Application of Formal Word-Level Analysis to Constrained Random Simulation
Abstract. Constrained random simulation is supported by constraint solvers integrated within simulators. These constraint solvers need to be fast and memory efficient to maintain s...
Hyondeuk Kim, HoonSang Jin, Kavita Ravi, Petr Spac...