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» Domain Reduction for the Circuit Constraint
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DATE
2008
IEEE
124views Hardware» more  DATE 2008»
14 years 1 months ago
Automated Testability Enhancements for Logic Brick Libraries
Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT ...
Jason G. Brown, Brian Taylor, Ronald D. Blanton, L...
ASPDAC
2008
ACM
87views Hardware» more  ASPDAC 2008»
13 years 9 months ago
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis
This paper proposes a novel Behavioral Synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional...
Tsuyoshi Sadakata, Yusuke Matsunaga
DAC
2005
ACM
13 years 9 months ago
Mixed signal design space exploration through analog platforms
We propose a hierarchical mixed signal design methodology based on the principles of Platform-Based Design (PBD). The methodology is a meet-in-the-middle approach where design com...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
TCAD
2002
73views more  TCAD 2002»
13 years 7 months ago
A timing-constrained simultaneous global routing algorithm
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
AI
2004
Springer
13 years 7 months ago
ASSAT: computing answer sets of a logic program by SAT solvers
We propose a new translation from normal logic programs with constraints under the answer set semantics to propositional logic. Given a normal logic program, we show that by addin...
Fangzhen Lin, Yuting Zhao