Sciweavers

173 search results - page 27 / 35
» Domain Reduction for the Circuit Constraint
Sort
View
DAC
2006
ACM
14 years 8 months ago
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sh...
TON
2008
95views more  TON 2008»
13 years 7 months ago
Integration of explicit effective-bandwidth-based QoS routing with best-effort routing
This paper presents a methodology for protecting low-priority best-effort (BE) traffic in a network domain that provides both virtual-circuit routing with bandwidth reservation for...
Stephen L. Spitler, Daniel C. Lee
ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 4 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani
SAC
2004
ACM
14 years 24 days ago
A new algorithm for gap constrained sequence mining
The sequence mining problem consists in finding frequent sequential patterns in a database of time-stamped events. Several application domains require limiting the maximum tempor...
Salvatore Orlando, Raffaele Perego, Claudio Silves...
TODAES
2002
134views more  TODAES 2002»
13 years 7 months ago
False-noise analysis using logic implications
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
Alexey Glebov, Sergey Gavrilov, David Blaauw, Vlad...