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» Domain Reduction for the Circuit Constraint
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CP
2010
Springer
13 years 6 months ago
A Complete Multi-valued SAT Solver
We present a new complete multi-valued SAT solver, based on current state-of-the-art SAT technology. It features watched literal propagation and conflict driven clause learning. W...
Siddhartha Jain, Eoin O'Mahony, Meinolf Sellmann
DAC
2007
ACM
14 years 8 months ago
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literatur...
Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 1 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
ICCAD
2006
IEEE
149views Hardware» more  ICCAD 2006»
14 years 1 months ago
Fast decap allocation based on algebraic multigrid
Decap (decoupling capacitor) is an effective technique for suppressing power supply noise. Nevertheless, over-usage of decap usually causes excessive power dissipation. Therefore...
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 7 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija