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» Domain Reduction for the Circuit Constraint
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CLEIEJ
2010
13 years 7 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
OTM
2007
Springer
14 years 3 months ago
Reduction Transformations in ORM
Abstract: This paper proposes extensions to the Object-Role Modeling approach to support schema transformations that eliminate unneeded columns that may arise from standard relatio...
Terry A. Halpin, Andy Carver, Kevin M. Owen
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
14 years 3 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
ICCAD
2002
IEEE
109views Hardware» more  ICCAD 2002»
14 years 6 months ago
Methods for true power minimization
This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of ...
Robert W. Brodersen, Mark Horowitz, Dejan Markovic...
AADEBUG
2000
Springer
14 years 2 months ago
Value Withdrawal Explanation in CSP
This work is devoted to constraint solving motivated by the debugging of constraint logic programs a la GNU-Prolog. The paper focuses only on the constraints. In this framework, c...
Gérard Ferrand, Willy Lesaint, Alexandre Te...