50 search results - page 5 / 10 » Dominator-based partitioning for delay optimization |
HPCA
2000
IEEE
14 years 6 hour ago
2000
IEEE
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip. Current superscalar processors have in fact a two-cluster mic...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
SIGMETRICS
2009
ACM
14 years 2 months ago
2009
ACM
We consider the problem of designing scheduling algorithms for the downlink of cellular wireless networks where bandwidth is partitioned into tens to hundreds of parallel channels...
HPCA
2000
IEEE
14 years 6 hour ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
ICDE
2005
IEEE
14 years 1 months ago
2005
IEEE
We pose the question: how do we efficiently evaluate a join operator, distributed over a heterogeneous network? Our objective here is to optimize the delay of output tuples. We di...