76 search results - page 3 / 16 » Doubled Patterns are 3-Avoidable |
DAC
2009
ACM
14 years 10 months ago
2009
ACM
In double patterning lithography (DPL), coloring conflict and stitch minimization are the two main challenges. Post layout decomposition algorithm [1] [2]may not be enough to achi...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
— Double patterning technology (DPT) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of Extreme Ultra Violet lithography. However, ...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...
ISPD
2010
ACM
14 years 4 months ago
2010
ACM
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...