21 search results - page 2 / 5 » Dynamic Base Register Caching: A Technique for Reducing Addr... |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
WECWIS
2002
IEEE
14 years 11 days ago
2002
IEEE
Various dynamic content caching approaches have been proposed to address the performance and scalability problems faced by many Web sites that utilize dynamic content generation a...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym proble...
ISCA
2010
IEEE
14 years 17 days ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
LCTRTS
2009
Springer
14 years 2 months ago
2009
Springer
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...