Sciweavers

207 search results - page 25 / 42
» Dynamic Cache Switching in Reconfigurable Embedded Systems
Sort
View
DAGSTUHL
2006
13 years 8 months ago
Reliability-Aware Power Management Of Multi-Core Systems (MPSoCs)
Long-term reliability of processors in embedded systems is experiencing growing attention since decreasing feature sizes and increasing power consumption have a negative influence...
Klaus Waldschmidt, Jan Haase, Andreas Hofmann, Mar...
ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 20 days ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
RTAS
1996
IEEE
13 years 11 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
AUTOMATICA
2008
89views more  AUTOMATICA 2008»
13 years 7 months ago
Dynamic buffer management using optimal control of hybrid systems
This paper studies a general dynamic buffer management problem with one buffer inserted between two interacting components. The component to be controlled is assumed to have multi...
Wei Zhang, Jianghai Hu
IASTEDSEA
2004
13 years 8 months ago
A component model for building systems software
OpenCOM v2 is our experimental language-independent component-based systems-building technology. OpenCOM offers more than merely a component-based programming model. First, it is ...
Geoff Coulson, Gordon S. Blair, Paul Grace, Ackbar...