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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 3 months ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
305views Hardware» more  ISCA 2010»
14 years 3 months ago
Rethinking DRAM design and organization for energy-constrained multi-cores
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
Aniruddha N. Udipi, Naveen Muralimanohar, Niladris...
ISCA
2010
IEEE
204views Hardware» more  ISCA 2010»
14 years 3 months ago
Energy proportional datacenter networks
Numerous studies have shown that datacenter computers rarely operate at full utilization, leading to a number of proposals for creating servers that are energy proportional with r...
Dennis Abts, Michael R. Marty, Philip M. Wells, Pe...
JCDL
2010
ACM
184views Education» more  JCDL 2010»
14 years 3 months ago
Evaluating topic models for digital libraries
Topic models could have a huge impact on improving the ways users find and discover content in digital libraries and search interfaces, through their ability to automatically lea...
David Newman, Youn Noh, Edmund M. Talley, Sarvnaz ...
HICSS
2002
IEEE
140views Biometrics» more  HICSS 2002»
14 years 2 months ago
Intelligent Student Profiling with Fuzzy Models
Traditional Web-based educational systems still have several shortcomings when comparing with a real-life classroom teaching, such as lack of contextual and adaptive support, lack...
Dongming Xu, Huaiqing Wang, Kaile Su
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