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HIPEAC
2010
Springer
14 years 7 months ago
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
John Sartori, Rakesh Kumar
ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
14 years 4 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...

Publication
156views
15 years 8 months ago
On Determining the Fair Bandwidth Share for ABR Connections in ATM Networks
In a multi-service network such as ATM, adaptive data services ( such as ABR) share the bandwidth left unused by higher priority services. The network indicates to the ABR sources ...
Sonia Fahmy, Raj Jain, Shivkumar Kalyanaraman, Roh...
SIPS
2007
IEEE
14 years 4 months ago
Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations
A hardware ef cient approach is introduced for elementary function evaluations in certain structured matrix computations. It is a comprehensive approach that utilizes lookup table...
Kanwaldeep Sobti, Lanping Deng, Chaitali Chakrabar...
SOCASE
2007
Springer
14 years 4 months ago
Executing Semantic Web Services with a Context-Aware Service Execution Agent
The need to add semantic information to web-accessible services has created a growing research activity in this area. Standard initiatives such as OWL-S and WSDL enable the automat...
António Lopes, Luís Miguel Botelho