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INFOCOM
1999
IEEE
13 years 12 months ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. ...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da...
CCGRID
2007
IEEE
13 years 11 months ago
Large Scale Deployment of Molecular Docking Application on Computational Grid infrastructures for Combating Malaria
Computational grids are solutions for several biological applications like virtual screening or molecular dynamics where large amounts of computing power and storage are required....
Vinod Kasam, Jean Salzemann, Nicolas Jacq, Astrid ...
ICC
2007
IEEE
201views Communications» more  ICC 2007»
13 years 11 months ago
TMMAC: An Energy Efficient Multi-Channel MAC Protocol for Ad Hoc Networks
This paper presents a TDMA based multi-channel MAC protocol called TMMAC for Ad Hoc Networks. TMMAC requires only a single half-duplex radio transceiver on each node. In addition t...
Jingbin Zhang, Gang Zhou, Chengdu Huang, Sang Hyuk...
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
13 years 11 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki
CASES
2001
ACM
13 years 11 months ago
Heads and tails: a variable-length instruction format supporting parallel fetch and decode
Abstract. Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and de...
Heidi Pan, Krste Asanovic