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ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 4 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
EUC
2008
Springer
13 years 9 months ago
Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment
This paper studies the scheduling and assignment problem that minimizes the total energy including both dynamic and leakage energy for applications with loops on multi-voltage, mul...
Meikang Qiu, Jiande Wu, Jingtong Hu, Yi He, Edwin ...
ISLPED
2010
ACM
165views Hardware» more  ISLPED 2010»
13 years 7 months ago
Dynamic workload characterization for power efficient scheduling on CMP systems
Runtime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems...
Gaurav Dhiman, Vasileios Kontorinis, Dean M. Tulls...
IPCCC
2006
IEEE
14 years 1 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
WINET
2010
158views more  WINET 2010»
13 years 5 months ago
Joint multi-cost routing and power control in wireless ad hoc networks
Abstract In this work we study the combination of multicost routing and adjustable transmission power in wireless ad hoc networks, so as to obtain dynamic energy- and interference-...
Nikolaos Karagiorgas, Panagiotis C. Kokkinos, Chri...