473 search results - page 39 / 95 » Dynamic Memory Design for Low Data-Retention Power |
CCECE
2009
IEEE
14 years 3 months ago
2009
IEEE
A workstation requires a low-power design similar to a typical PC. In this paper we propose several strategies to reduce the power consumption of a workstation. First, we must com...
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
WMPI
2004
ACM
14 years 2 months ago
2004
ACM
Current trends suggest that the number of memory chips per processor chip will increase at least a factor of ten in seven years. This will make DRAM cost, the space and the power i...
VEE
2006
ACM
14 years 2 months ago
2006
ACM
Software Dynamic Translation (SDT) systems have been used for program instrumentation, dynamic optimization, security policy enforcement, intrusion detection, and many other uses....