473 search results - page 48 / 95 » Dynamic Memory Design for Low Data-Retention Power |
FAST
2011
13 years 7 days ago
2011
Multi-tier systems that combine SSDs with SAS/FC and/or SATA disks mitigate the capital cost burden of SSDs, while benefiting from their superior I/O performance per unit cost an...
ARCS
2004
Springer
14 years 14 days ago
2004
Springer
: This paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamical...
CODES
2008
IEEE
13 years 10 months ago
2008
IEEE
Memory subsystems have been considered as one of the most critical components in embedded systems and furthermore, displaying increasing complexity as application requirements div...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
ASPDAC
2005
ACM
14 years 2 months ago
2005
ACM
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...