473 search results - page 49 / 95 » Dynamic Memory Design for Low Data-Retention Power |
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...
DATE
2004
IEEE
14 years 14 days ago
2004
IEEE
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
INFOCOM
2012
IEEE
11 years 11 months ago
2012
IEEE
—This paper considers a component-level deceleration technique in BS operation, called speed-scaling, that is more conservative than entirely shutting down BSs, yet can conserve ...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...