473 search results - page 74 / 95 » Dynamic Memory Design for Low Data-Retention Power |
BIBE
2007
IEEE
14 years 3 months ago
2007
IEEE
Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course- and fine-grain parallelization. A ...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an e...
OSDI
2002
ACM
14 years 9 months ago
2002
ACM
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...
HIPEAC
2009
Springer
14 years 17 days ago
2009
Springer
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
Previous work on DRAM power-mode management focused on hardware-based techniques and compiler-directed schemes to explicitly transition unused memory modules to low-power operatin...