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» Dynamic Memory Design for Low Data-Retention Power
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ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
14 years 1 months ago
A tunable bus encoder for off-chip data buses
Off-Chip buses constitute a significant portion of the total system power in embedded systems. Past research has focused on encoding contiguous bit positions in data values to red...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
HPCA
2012
IEEE
12 years 3 months ago
Flexible register management using reference counting
Conventional out-of-order processors that use a unified physical register file allocate and reclaim registers explicitly using a free list that operates as a circular queue. We ...
Steven Battle, Andrew D. Hilton, Mark Hempstead, A...
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 1 months ago
Late-binding: enabling unordered load-store queues
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
Simha Sethumadhavan, Franziska Roesner, Joel S. Em...
CIKM
2009
Springer
14 years 5 days ago
Low-cost management of inverted files for online full-text search
In dynamic environments with frequent content updates, we require online full-text search that scales to large data collections and achieves low search latency. Several recent met...
Giorgos Margaritis, Stergios V. Anastasiadis
SIGSOFT
2003
ACM
14 years 8 months ago
Protecting C programs from attacks via invalid pointer dereferences
Writes via unchecked pointer dereferences rank high among vulnerabilities most often exploited by malicious code. The most common attacks use an unchecked string copy to cause a b...
Suan Hsi Yong, Susan Horwitz