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» Dynamic Partial Reconfigurable FIR Filter Design
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ERSA
2006
99views Hardware» more  ERSA 2006»
13 years 8 months ago
Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
Muhammad Akhtar Khan, Abdul Hameed, Ahmet T. Erdog...
TIM
2010
188views Education» more  TIM 2010»
13 years 2 months ago
An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems
Abstract--The most popular representative devices of reconfigurable computing are the Field Programmable Gate Arrays (FPGAs). A promising feature of an FPGA is the ability to reuse...
Kyprianos Papadimitriou, Antonis Anyfantis, Aposto...
ASPDAC
2008
ACM
164views Hardware» more  ASPDAC 2008»
13 years 9 months ago
The Shining embedded system design methodology based on self dynamic reconfigurable architectures
Complex design, targeting System-on-Chip based on reconfigurable architectures, still lacks a generalized methodology allowing both the automatic derivation of a complete system s...
Carlo Curino, Luca Fossati, Vincenzo Rana, Frances...
ARCS
2005
Springer
14 years 1 months ago
An FPGA Dynamically Reconfigurable Framework for Modular Robotics
Dynamic Reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting...
Andres Upegui, Rico Moeckel, Elmar Dittrich, Auke ...
ARCS
2006
Springer
13 years 11 months ago
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro
Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial...
Christopher Claus, Florian Helmut Müller, Wal...