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HPCA
2005
IEEE
14 years 1 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
CLUSTER
2004
IEEE
13 years 11 months ago
A client-centric grid knowledgebase
Grid computing brings with it additional complexities and unexpected failures. Just keeping track of our jobs traversing different grid resources before completion can at times be...
George Kola, Tevfik Kosar, Miron Livny
ICDE
2009
IEEE
200views Database» more  ICDE 2009»
14 years 9 months ago
Adaptive Scheduling of Web Transactions
In highly interactive dynamic web database systems, user satisfaction determines their success. In such systems, userrequested web pages are dynamically created by executing a numb...
Shenoda Guirguis, Mohamed A. Sharaf, Panos K. Chry...
FTDCS
1995
IEEE
13 years 11 months ago
A Network Channel Buffer Scheduling Algorithm for an Interactive VOD Server
A VOD server handles various types of media such as continuous media (CM) and non-continuous media (NM). Conventional VOD server buffer scheduling algorithms like Round Robin (RR)...
Sungyoung Lee, Hyungill Kim, Jongwon Lee
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 5 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou