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» Dynamic Power Management Using Data Buffers
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ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
14 years 4 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 4 months ago
SPM management using Markov chain based data access prediction
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
IOPADS
1997
152views more  IOPADS 1997»
13 years 9 months ago
Competitive Parallel Disk Prefetching and Buffer Management
We provide a competitive analysis framework for online prefetching and buffer management algorithms in parallel I/O systems, using a read-once model of block references. This has ...
Rakesh D. Barve, Mahesh Kallahalla, Peter J. Varma...

Publication
255views
15 years 6 months ago
Buffer Management and Rate Guarantees for TCP/IP over Satellite-ATM Networks
Future broadband satellite networks will support a variety of service types. Many such systems are being designed with ATM or ATM like technology. A majority of Internet applicatio...
Rohit Goyal, Raj Jain, Mukul Goyal, Sonia Fahmy, B...
EUROPAR
2010
Springer
13 years 9 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...