1815 search results - page 28 / 363 » Dynamic Power Management Using Data Buffers |
ANCS
2007
ACM
13 years 12 months ago
2007
ACM
We propose a distributed congestion management scheme for non-blocking, 3-stage Clos networks, comprising plain buffered crossbar switches. VOQ requests are routed using multipath...
IEEEPACT
2002
IEEE
14 years 26 days ago
2002
IEEE
Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, ...
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
MICRO
2008
IEEE
14 years 2 months ago
2008
IEEE
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...