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» Dynamic Power Management Using Data Buffers
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VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
14 years 8 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
14 years 1 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
HICSS
2007
IEEE
85views Biometrics» more  HICSS 2007»
14 years 2 months ago
Leveraging Computational Grid Technologies for Building a Secure and Manageable Power Grid
The US Power Industry is in the process of overhauling the Power Grid to make it more secure, reliable, and available. The IT systems that comprise a major part of this change nee...
Himanshu Khurana, Mohammad Maifi Hasan Khan, Von W...
ICC
2008
IEEE
117views Communications» more  ICC 2008»
14 years 2 months ago
Proactive Power Optimization of Sensor Networks
—We propose a reduced-complexity genetic algorithm for dynamic deployment of resource constrained multi-hop mobile sensor networks. The goal of this paper is to achieve optimal c...
Rahul Khanna, Huaping Liu, Hsiao-Hwa Chen
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
13 years 11 months ago
Low Static-Power Frequent-Value Data Caches
: Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics ...
Chuanjun Zhang, Jun Yang 0002, Frank Vahid