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» Dynamic Power Management Using Data Buffers
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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
VLDB
1998
ACM
199views Database» more  VLDB 1998»
14 years 2 days ago
The ADABAS Buffer Pool Manager
The buffer pool manager is a central component of ADABAS, a high performance scaleable database system for OLTP processing. High efficiency and scalability of the buffer pool mana...
Harald Schöning
DAC
2005
ACM
14 years 8 months ago
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
King Ho Tam, Lei He
ASPDAC
2000
ACM
120views Hardware» more  ASPDAC 2000»
14 years 7 days ago
Data memory minimization by sharing large size buffers
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
Hyunok Oh, Soonhoi Ha
LCTRTS
2000
Springer
13 years 11 months ago
An Integrated Push/Pull Buffer Management Method in Multimedia Communication Environments
Multimedia communication systems require not only high-performance computer hardware and highspeed networks, but also a buffer management mechanism to process voluminous data effi...
Sungyoung Lee, Hyonwoo Seung, Taewoong Jeon