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JILP
2000
109views more  JILP 2000»
13 years 7 months ago
Dynamic Register Renaming Through Virtual-Physical Registers
Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instructio...
Teresa Monreal, Antonio González, Mateo Val...
LCPC
2005
Springer
14 years 27 days ago
Manipulating MAXLIVE for Spill-Free Register Allocation
Abstract. Many embedded systems use single-chip microcontrollers which have no on-chip RAM. In such a system, the processor registers must hold all live data values. Nanocontroller...
Shashi Deepa Arcot, Henry G. Dietz, Sarojini Priya...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
LCTRTS
2005
Springer
14 years 27 days ago
Syncopation: generational real-time garbage collection in the metronome
Real-time garbage collection has been shown to be feasible, but for programs with high allocation rates, the utilization achievable is not sufficient for some systems. Since a hi...
David F. Bacon, Perry Cheng, David Grove, Martin T...
ANCS
2008
ACM
13 years 9 months ago
On runtime management in multi-core packet processing systems
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing system...
Qiang Wu, Tilman Wolf