Sciweavers

74 search results - page 7 / 15
» Dynamic Reallocation of Functional Units in Superscalar Proc...
Sort
View
LCTRTS
2001
Springer
14 years 1 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
14 years 21 days ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
MICRO
1994
IEEE
96views Hardware» more  MICRO 1994»
14 years 21 days ago
A fill-unit approach to multiple instruction issue
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
Manoj Franklin, Mark Smotherman
EUROMICRO
1999
IEEE
14 years 27 days ago
Delft-Java Dynamic Translation
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
C. John Glossner, Stamatis Vassiliadis
TVLSI
2010
13 years 3 months ago
On the Power Management of Simultaneous Multithreading Processors
SMT processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is sig...
Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed...