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ASPLOS
2008
ACM
13 years 9 months ago
SoftSig: software-exposed hardware signatures for code analysis and optimization
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas
MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
13 years 12 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
CVPR
2011
IEEE
13 years 2 months ago
Intrinsic Dense 3D Surface Tracking
This paper presents a novel intrinsic 3D surface distance and its use in a complete probabilistic tracking framework for dynamic 3D data. Registering two frames of a deforming 3D ...
Yun Zeng, Chaohui Wang, Yang Wang, David Gu, Dimit...
ISMAR
2002
IEEE
14 years 20 days ago
Practical Solutions for Calibration of Optical See-Through Devices
One of the most crucial tasks in a see-through augmented reality (AR) system is to register the virtual objects with the real world through a transparent display. The importance s...
Yakup Genc, Mihran Tuceryan, Nassir Navab
PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 1 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...