Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
Shervin Sharifi, Javid Jaffari, Mohammad Hosseinab...
Interactive multimediaapplicationsrequire fast response time. Traditional disk scheduling schemes can incur high latencies, and caching data in memory to reduce latency is usually...
A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-d...
Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. R...
Abstract. Linear scan register allocation is an attractive register allocation algorithm because of its simplicity and fast running time. However, it is generally felt that linear ...
suitable disk layout and network transmission schedule to minimize allocated resources (buffer size, bandwidth, ..., etc.) with maximum resource utilization. In this paper, the rea...