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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 14 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ICS
2001
Tsinghua U.
13 years 12 months ago
Global optimization techniques for automatic parallelization of hybrid applications
This paper presents a novel technique to perform global optimization of communication and preprocessing calls in the presence of array accesses with arbitrary subscripts. Our sche...
Dhruva R. Chakrabarti, Prithviraj Banerjee
INFOCOM
2000
IEEE
13 years 11 months ago
Fair Bandwidth Sharing Among Virtual Networks: A Capacity Resizing Approach
Abstract—Virtual Private Networks (VPN) and link sharing are cost effective way of realizing corporate intranets. Corporate intranets will increasingly have to provide Integrated...
Rahul Garg, Huzur Saran
INFOCOM
1999
IEEE
13 years 11 months ago
An Effective and Efficient Traffic Smoothing Scheme for Delivery of Online VBR Media Streams
Traffic smoothing for delivery of online VBR media streams is one of the most important problems in designing multimedia systems. Given available client buffer and a window-slidin...
Ray-I Chang, Meng Chang Chen, Jan-Ming Ho, Ming-Ta...
IPPS
1999
IEEE
13 years 11 months ago
Process Networks as a High-Level Notation for Metacomputing
Abstract. Our work involves the development of a prototype Geographical Information System GIS as an example of the use of process networks as a well-de ned high-level semantic mod...
Darren Webb, Andrew L. Wendelborn, Kevin Maciunas