10 search results - page 2 / 2 » Dynamic Self-Invalidation: Reducing Coherence Overhead in Sh... |
CF
2007
ACM
13 years 11 months ago
2007
ACM
In this work we reduce interconnect power dissipation in Symmetric Multiprocessors or SMPs. We revisit snoopy cache coherence protocols and reduce unnecessary interconnect activit...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...
IPPS
2000
IEEE
13 years 12 months ago
2000
IEEE
In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following ...
IPPS
2003
IEEE
14 years 22 days ago
2003
IEEE
OpenMP has emerged as a widely accepted standard for writing shared memory programs. Hardware-specific extensions such as data placement are usually needed to improve the scalabi...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...