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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 26 days ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
ASPLOS
2006
ACM
14 years 1 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
UIST
2004
ACM
14 years 1 months ago
SketchREAD: a multi-domain sketch recognition engine
We present SketchREAD, a multi-domain sketch recognition engine capable of recognizing freely hand-drawn diagrammatic sketches. Current computer sketch recognition systems are dif...
Christine Alvarado, Randall Davis
PROMISE
2010
13 years 2 months ago
Defect cost flow model: a Bayesian network for predicting defect correction effort
Background. Software defect prediction has been one of the central topics of software engineering. Predicted defect counts have been used mainly to assess software quality and est...
Thomas Schulz, Lukasz Radlinski, Thomas Gorges, Wo...
IEEEPACT
2007
IEEE
14 years 1 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick