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» Dynamic Voltage and Cache Reconfiguration for Low Power
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RTAS
2005
IEEE
14 years 28 days ago
Practical On-line DVS Scheduling for Fixed-Priority Real-Time Systems
We present an on-line Dynamic Voltage Scaling (DVS) algorithm for preemptive fixed-priority real-time systems called low power Limited Demand Analysis with Transition overhead (l...
Bren Mochocki, Xiaobo Sharon Hu, Gang Quan
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 19 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
GLOBECOM
2007
IEEE
13 years 9 months ago
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, And...
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
14 years 1 days ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
IPPS
2007
IEEE
14 years 1 months ago
Scaling and Packing on a Chip Multiprocessor
Power management is critical in server and high-performancecomputing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support ...
Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Raw...