53 search results - page 3 / 11 » Dynamic instruction schedulers in a 3-dimensional integratio... |
RTAS
2003
IEEE
13 years 12 months ago
2003
IEEE
Wireless and portable devices depend on the limited power supplied by the battery. Dynamic Voltage Scaling (DVS) is an effective method to reduce CPU power consumption. For real-t...
ISCAPDCS
2004
13 years 8 months ago
2004
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
WSC
2001
13 years 8 months ago
2001
This paper presents a hierarchical approach on the simulation of large-scale discrete event systems used recently by Kiran Consulting Group (KCG) to model shipyard operations. Bec...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
PDPTA
2000
13 years 8 months ago
2000
Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrat...