50 search results - page 7 / 10 » Dynamic overlay of scratchpad memory for energy minimization |
ISCA
2012
IEEE
12 years 24 days ago
2012
IEEE
Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operation...
ISLPED
2010
ACM
13 years 10 months ago
2010
ACM
Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
MICRO
2005
IEEE
14 years 4 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
HIPC
2007
Springer
14 years 4 months ago
2007
Springer
- With the increased complexity of platforms coupled with data centers’ servers sprawl, power consumption is reaching unsustainable limits. Memory is an important target for plat...