4 search results - page 1 / 1 » Dynamic power minimization during combinational circuit test... |
CEC
2005
IEEE
14 years 2 months ago
2005
IEEE
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
FLAIRS
2006
13 years 10 months ago
2006
We propose a real time single item auction based task allocation method for the multi-robot exploration problem and investigate new bid evaluation strategies in this domain. In th...
ICCAD
2010
IEEE
13 years 6 months ago
2010
IEEE
Reducing circuit's peak current plays an important role in circuit reliability in deep sub-micron era. For sequential circuits, it is observed that the peak current has a str...