65 search results - page 4 / 13 » Dynamic power-performance adaptation of parallel computation... |
DSN
2007
IEEE
14 years 2 months ago
2007
IEEE
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
EUROPAR
2008
Springer
13 years 9 months ago
2008
Springer
Recent studies have showed the effectiveness of job co-scheduling in alleviating shared-cache contention on Chip Multiprocessors. Although program inputs affect cache usage and thu...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Power management is critical in server and high-performancecomputing environments as well as in mobile computing. Many mechanisms have been developed over recent years to support ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...