329 search results - page 56 / 66 » Dynamic techniques to reduce memory traffic in embedded syst... |
SBRN
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper proposes a simple methodology to construct an iterative neural network which mimics a given chaotic time series. The methodology uses the Gamma test to identify a suita...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
OSDI
2002
ACM
14 years 7 months ago
2002
ACM
This paper shows how to quickly move the state of a running computer across a network, including the state in its disks, memory, CPU registers, and I/O devices. We call this state...
VLSID
2001
IEEE
14 years 7 months ago
2001
IEEE
The need for low-power multimedia processing is integral to portable and embedded devices such as cell phones, wireless terminals, multimedia handhelds and PDAs. The multimedia pr...
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applic...