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» Dynamic thermal management in 3D multicore architectures
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MICRO
2005
IEEE
113views Hardware» more  MICRO 2005»
14 years 2 months ago
Thermal Management of On-Chip Caches Through Power Density Minimization
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I....
DAC
2006
ACM
13 years 10 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
DAC
2009
ACM
14 years 3 months ago
On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration
With new technologies, temperature has become a major issue to be considered at system level design. Without taking temperature aspects into consideration, no approach to energy o...
Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
14 years 1 months ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...
ASPLOS
2008
ACM
13 years 10 months ago
Adapting to intermittent faults in multicore systems
Future multicore processors will be more susceptible to a variety of hardware failures. In particular, intermittent faults, caused in part by manufacturing, thermal, and voltage v...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...