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SOSP
2001
ACM
14 years 3 months ago
Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems
In recent years, there has been a rapid and wide spread of nontraditional computing platforms, especially mobile and portable computing devices. As applications become increasingl...
Padmanabhan Pillai, Kang G. Shin
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
14 years 3 months ago
Post-placement voltage island generation
High power consumption will shorten battery life for handheld devices and cause thermal and reliability problems. One way to lower the dynamic power consumption is to reduce the s...
Royce L. S. Ching, Evangeline F. Y. Young, Kevin C...
VLSID
1996
IEEE
153views VLSI» more  VLSID 1996»
13 years 11 months ago
Design of high performance two stage CMOS cascode op-amps with stable biasing
The technique of mirror biasing is introduced and applied to a very high gain two stage CMOS cascode op-amp, in order to desensitize its output voltage to bias variations. Various...
Pradip Mandal, V. Visvanathan
PLDI
2003
ACM
13 years 12 months ago
Compile-time dynamic voltage scaling settings: opportunities and limits
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
Fen Xie, Margaret Martonosi, Sharad Malik
GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
14 years 16 hour ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi