40 search results - page 4 / 8 » Dynamic zero compression for cache energy reduction |
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
ICRA
2009
IEEE
14 years 2 months ago
2009
IEEE
— The influence of ankle compliance on bipedal robot locomotion is investigated in this paper. The focus is on reduction of energy consumption. The concept of hybrid zero dynami...
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
CSREAESA
2003
13 years 9 months ago
2003
Energy dissipation in cache memories is becoming a major design issue in embedded microprocessors. Predictive filter cache based instruction cache hierarchy is effective in reduci...
SBCCI
2005
ACM
14 years 1 months ago
2005
ACM
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...