Sciweavers

234 search results - page 34 / 47
» Dynamically Reconfigurable Vision-Chip Architecture
Sort
View
DSN
2004
IEEE
14 years 2 months ago
Efficient Hierarchic Management For Reconfiguration of Networked Information Systems
The management of modern distributed systems is complicated by scale and dynamics. Scalable, decoupled communication establishes flexible, loosely coupled component relationships,...
Jonathan C. Rowanhill, Philip E. Varner, John C. K...
DAGSTUHL
2009
13 years 12 months ago
Using Architecture Models to Support the Generation and Operation of Component-Based Adaptive Systems
Modelling architectural information is particularly important because of the acknowledged crucial role of software architecture in raising the level of abstraction during developme...
Nelly Bencomo, Gordon S. Blair
IWIA
2005
IEEE
14 years 4 months ago
A General Cooperative Intrusion Detection Architecture for MANETs
1 Intrusion detection in MANETs is challenging because these networks change their topologies dynamically; lack concentration points where aggregated traffic can be analyzed; utili...
Daniel F. Sterne, Poornima Balasubramanyam, David ...
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
14 years 27 days ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler
ERSA
2006
100views Hardware» more  ERSA 2006»
14 years 9 days ago
Relocation and Defragmentation for Heterogeneous Reconfigurable Systems
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
Markus Koester, Heiko Kalte, Mario Porrmann