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DAC
2005
ACM
14 years 8 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
RECOSOC
2007
118views Hardware» more  RECOSOC 2007»
13 years 9 months ago
A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems
Electronic equipments with higher performance, lower power consumption, and smaller size motivate the research for more efficient design methods. Platform-based design is a method...
Leandro Möller, Ismael Grehs, Ewerson Carvalh...
ICETET
2009
IEEE
13 years 5 months ago
High Performance WDM Using Semiconductor Tunable Laser
Advances in optical networking have lead to the explosive growth of communication network. Telecom applications began to drive significant investments into this field to support t...
S. S. Agrawal, K. D. Kulat, M. B. Daigavane
ICS
2009
Tsinghua U.
14 years 5 days ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 1 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky