130 search results - page 15 / 26 » Dynamically Scheduling VLIW Instructions |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
The load instructions of some of the bioinformatics applications in the BioPerf suite possess interesting characteristics: only a few static loads cover almost the entire dynamic ...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
Accelerating program performance via SIMD vector units is very common in modern processors, as evidenced by the use of SSE, MMX, VSE, and VSX SIMD instructions in multimedia, scien...
ISCA
2002
IEEE
14 years 12 days ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...