130 search results - page 17 / 26 » Dynamically Scheduling VLIW Instructions |
RTSS
1999
IEEE
13 years 11 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
We introduce techniques to support efficient non-atomic execution of very long traces on a new binary translation based, x86-64 compatible VLIW microprocessor. Incrementally comm...
IEEEPACT
1999
IEEE
13 years 11 months ago
1999
IEEE
An asynchronous superscalar architecture is presented based on a novel architectural feature called instruction compounding. This enables efficient dynamic scheduling and forwardi...
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...