130 search results - page 5 / 26 » Dynamically Scheduling VLIW Instructions |
CF
2004
ACM
14 years 26 days ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Many studies have investigated performance improvement through exploiting instruction-level parallelism (ILP) with a particular architecture. Unfortunately, these studies indicate...
HICSS
1995
IEEE
13 years 11 months ago
1995
IEEE
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
TVLSI
2002
13 years 7 months ago
2002
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
TCAD
2002
13 years 7 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...